Systemverilog for Design: A Guide to Using Systemverilog for Hardware Design and Modeling

by Stuart Sutherland

In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

448 pages, Hardcover

First published June 30, 2003

About the author

Mr. Stuart Sutherland is the founder and a principal engineer of Sutherland HDL, Inc., located in Portland Oregon. Sutherland HDL provides expert Verilog, SystemVerilog, UVM, SVA, and PLI/VPI/DPI training and consulting services.

Reviews

[Jaime Arias Almeida · Rating 5 out of 5]

It's an excellent book!.