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Logic Synthesis Using Synopsys®
Pran Kurup
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Foreword. Preface. 1. High-Level Design Methodology Overview. 2. Coding in HDL for Synthesis. 3. Pre and Post Synthesis Simulation. 4. Constraining and Optimizing Designs - I. 5. Constraining and Optimizing Designs - II. 6. Design for Testability. 7. Interfacing between CAD Tools. 8. Design Re-Use Using DesignWare. Appendix A. 1. Sample dc-shell scripts. 2. Using Synopsys On-Line Documentation - iview. 3. Synopsys Technology Library. 4. Sample Synopsys Technology Library RAM Model. References. Index.
328 pages, Paperback
Published February 14, 2013
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Pran Kurup
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