SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling

by Stuart Sutherland

1: Introduction to SystemVerilog.- 2: SystemVerilog Literal Values and Built-in Data Types.- 3: SystemVerilog User-Defined and Enumerated Data Types.- 4: SystemVerilog Arrays, Structures and Unions.- 5: SystemVerilog Procedural Blocks, Tasks and Functions.- 6: SystemVerilog Procedural Statements.- 7: Modeling Finite State Machines with SystemVerilog.- 8: SystemVerilog Design Hierarchy.- 9: SystemVerilog Interfaces.- 10: A Complete Design Modeled with SystemVerilog.- 11: Behavioral and Transaction Level Modeling.- Appendix The SystemVerilog Formal Definition (BNF).- Appendix A History of SUPERLOG, The Beginning of SystemVerilog.

404 pages, Paperback

First published June 30, 2003

About the author

Mr. Stuart Sutherland is the founder and a principal engineer of Sutherland HDL, Inc., located in Portland Oregon. Sutherland HDL provides expert Verilog, SystemVerilog, UVM, SVA, and PLI/VPI/DPI training and consulting services.

Reviews

[Jaime Arias Almeida · Rating 5 out of 5]

It's an excellent book!.