Compilation Techniques for Reconfigurable Architectures

by João M.P. Cardoso, Pedro C. Diniz

The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.

235 pages, Hardcover

First published November 2, 1979

About the author

João Manuel Paiva Cardoso.

I have been, since September 4th 2008, Associate Professor in the Department of Informatics Engineering (DEI), Faculty of Engineering, University of Porto, Porto, Portugal.

Before, I was Assistant Professor in the Department of Computer Science and Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon (UTL), in Lisbon (April 4, 2006- Sept. 3, 2008), and Assistant Professor (2001-2006) in the Department of Electronics and Informatics Engineering (DEEI), Faculty of Sciences and Technology, at the University of Algarve, and Teaching Assistant in the same university (1993-2001). I have been a senior researcher at INESC-ID (Systems and Computer Engineering Institute) in Lisbon. I was member of INESC-ID from 1994 to 2009.

I received a PhD and an MSc degree in Electrical and Computer Engineering both from the IST in 2001 and 1997, respectively, and a 5-year engineering degree in Electronic and Telecommunications from the University of Aveiro in 1993.

I worked during one year (2001-2002) for PACT XPP Technologies, Inc., Munich, Germany. There I participated in the research and development of the C compiler (XPP-VC) for the eXtreme Processing Platform (XPP), a coarse-grained reconfigurable computing architecture.

I am a member of the steering committee of the International Workshop on Applied Reconfigurable Computing (ARC). During recent years, I was general co-chair of ARC 2006, held in Delft, The Netherlands, March 1-3, 2006; program chair of ARC 2005, held in Algarve, Portugal, February 22-23, 2005; and general co-chair of the Jornadas sobre Sistemas Reconfiguráveis (REC 2005), a scientific meeting to discuss reconfigurable systems among Portuguese researchers. I was topic co-chair for “Design Methods and Tools” of FPL’2008, co-chair of the PhD forum of FPL’2007, and Exhibition/Sponsorship Chair of FPL’2003. I have been serving on various International Conferences as a Program Committee member and as a reviewer.

My research interests include: Compiler Techniques, Reconfigurable Computing Platforms and Tools, and Design Automation for Embedded Systems.

I am a Member of the IEEE, IEEE Computer Society and a Senior Member of ACM.