Arithmetic Built-In Self-Test for Embedded Systems

by Janusz Rajski, Jerzy Tyszer

Describes the software-based, built-in, self-testing for systems with embedded processors that engineers are increasingly using as early as possible in the design process to prevent costly prototyping turns. Offers tutorials, schemes to generate tests employing adders and multipliers, an accumulator-based scheme for the parallel compaction of test responses, fault simulation techniques, and applications. Annotation c. by Book News, Inc., Portland, Or.

268 pages, Hardcover

First published October 1, 1997