Compilation Techniques for Reconfigurable Architectures

by João M.P. Cardoso, Pedro C. Diniz

Describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. This book provides a structure for practitioners and graduate students in the area of computer science and electrical engineering to map computations to those architectures.

Contents:

Chapter 1: Introduction;
Chapter 2: Overview of Reconfigurable Architectures;
Chapter 3: Compilation and Synthesis Flows;
Chapter 4: Code Transformations;
Chapter 5: Mapping and Execution Optimizations;
Chapter 6: Compilers for Reconfigurable Architectures;
Chapter 7: Perspectives on Programming Reconfigurable Computing Platforms;
Chapter 8: Final Remarks;

23 pages, Paperback

First published November 2, 1979

About the author

João Manuel Paiva Cardoso.

I have been, since September 4th 2008, Associate Professor in the Department of Informatics Engineering (DEI), Faculty of Engineering, University of Porto, Porto, Portugal.

Before, I was Assistant Professor in the Department of Computer Science and Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon (UTL), in Lisbon (April 4, 2006- Sept. 3, 2008), and Assistant Professor (2001-2006) in the Department of Electronics and Informatics Engineering (DEEI), Faculty of Sciences and Technology, at the University of Algarve, and Teaching Assistant in the same university (1993-2001). I have been a senior researcher at INESC-ID (Systems and Computer Engineering Institute) in Lisbon. I was member of INESC-ID from 1994 to 2009.

I received a PhD and an MSc degree in Electrical and Computer Engineering both from the IST in 2001 and 1997, respectively, and a 5-year engineering degree in Electronic and Telecommunications from the University of Aveiro in 1993.

I worked during one year (2001-2002) for PACT XPP Technologies, Inc., Munich, Germany. There I participated in the research and development of the C compiler (XPP-VC) for the eXtreme Processing Platform (XPP), a coarse-grained reconfigurable computing architecture.

I am a member of the steering committee of the International Workshop on Applied Reconfigurable Computing (ARC). During recent years, I was general co-chair of ARC 2006, held in Delft, The Netherlands, March 1-3, 2006; program chair of ARC 2005, held in Algarve, Portugal, February 22-23, 2005; and general co-chair of the Jornadas sobre Sistemas Reconfiguráveis (REC 2005), a scientific meeting to discuss reconfigurable systems among Portuguese researchers. I was topic co-chair for “Design Methods and Tools” of FPL’2008, co-chair of the PhD forum of FPL’2007, and Exhibition/Sponsorship Chair of FPL’2003. I have been serving on various International Conferences as a Program Committee member and as a reviewer.

My research interests include: Compiler Techniques, Reconfigurable Computing Platforms and Tools, and Design Automation for Embedded Systems.

I am a Member of the IEEE, IEEE Computer Society and a Senior Member of ACM.