A Verilog HDL Primer

by Jayaram Bhasker

Written for new users.

Explains the language through simple examples.

Explains the syntax of language using commonly-used design terminology.

Explains the behavioral style, the dataflow style, and structural style in detail.

Concepts of delay and timing are clearly explained.

Testbench writing is made easier by providing a number of examples.

Many hardware modeling examples have also been provided to make this an excellent reference.

259 pages, Hardcover

First published March 1, 1997

Reviews

[Ashoke Chakraborty]

first let me read the book before any comments