The Verilog programming language interface is a powerful feature of the Verilog standard. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired, such as adding custom design debug utilities, adding proprietary file read/write utilities and interfacing bus functional C language models to a simulator.
Mr. Stuart Sutherland is the founder and a principal engineer of Sutherland HDL, Inc., located in Portland Oregon. Sutherland HDL provides expert Verilog, SystemVerilog, UVM, SVA, and PLI/VPI/DPI training and consulting services.