Applied Formal Verification

by Douglas L. Perry, Harry D. Foster

Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve real-world design problems. Contents: Simulation-Based Verification * Introduction to Formal Techniques * Contrasting Simulation vs. Formal Techniques * Developing a Formal Test Plan * Writing High-Level Requirements * Proving High-Level Requirements * System Level Simulation * Design Example * Formal Test Plan * Final System Simulation

256 pages, Hardcover

First published April 19, 2005

Reviews

[Rui Chen · Rating 3 out of 5]

It is a fairly good book, but lack of adequate examples. Along with my reading, some minor errors, like errors in 6.2.1 LTL logic, make me uncomfortable. Nearly a quarter of the whole book is dedicated to the PSL and SVA. I think it is just a introduction and easy-to-read formal verification book without much maths involved.