SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

by Christian B. Spear

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

465 pages, Paperback

First published July 17, 2008

Reviews

[Kari Ross · Rating 5 out of 5]

God help me, I'm reading this book cover to cover, although not in order. Even though I've been using SystemVerilog for years, we are using a very advanced testbench at work and this book is helping out tremendously. However dull to read.