VHDL SYNTHESIS PRIMER, 2ND EDITION

by Jayaram Bhasker

Here is a practical and useful guide to VHDL synthesis. The purpose of this book is to explain the transformations that occur during the synthesis process from a VHDL model to a netlist. Constructs that are supported for synthesis are clearly explained with many examples with their synthesized netlists.

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First published October 1, 1996