My gargantuan Second Edition of Mssrs. Patterson et Hennessy, reeking with the stench of death forever associated with CS2200 (the foulest corruption of awesome material via wretched undergraduate TA fuckups 'ere I've experienced), sits off in the corner of my room, 1100+ pages of processing, parallelizing, and pipelining. When I found problems assigned to our CS6290 (High-Performance Computer Architecture) class last week out of the Fourth Edition, and that -- of course -- the exercises had been changed across editions (even if nothing else), I was plenty pissed off. I mean, come on, one of the authors is president of Stanford (and designed MIPS); the other was president of ACM and tenured at UCB (and had his hands in SPARC). I'm by no means a starving undergraduate, but I was in no way thrilled to find myself owing P&H yet another $100. To add insult to injury, this fourth edition had regressed to paperback, and slimmed down by some 600 pages. Overcoming the urge to firebomb GTB&N, I went home to LaTeX up problems 1-11 and 1-13, and find a good Unibomber jacket.
Lo, this is one of the most inspired revisions I've ever seen -- ranking with Knuth's Third, K&R's Second, or the Second as well of Abelman and Sussman (note that Dijkstra never needed more than a first (zeroth) edition -- one merely rereads A Discipline of Programming every few years and gazes back in wonder at time wasted in foolishness). The exercises have indeed been completely redone. Yes, this is normally a cause for groans and the gnashing of teeth -- the goal of invalidating previous years' and other colleges' homeworks is met, at the cost of a revue derelictia, a comedy of errors; graduate students, their ESL skills underwhelmed only by their bewilderment when handed practical tasks, cut swaths of inconsistent, incomprehensible furrow into previously-useful exercise sets -- like the great Midwestern tornadoes, they're with us only for a moment and leave naught but chaos, confusion and strewn papers in their wake. P&H have taken time out of their busy Stanford-pimping schedules to instead lovingly parameterize their exercises, presumably in combination with generators for all things Presentation, and intend to release re-parameterized sets each year (semester?) -- in this way, we assume, the motivator for new editions and thus costs is eliminated (0). This is noble, although it immediately sets a fine challenge to the motivated student: produce fully parameterized solutions to the problems, capable of taking the definition as input and generating the correct instance of output =]. In the immortal words of Tannenbaum's Structured Computer Organization (Fourth Edition): "At the end of this chapter the motivated student ought be able to leave his home, purchase a bag of transistors, and implement the PicoJavaII. Students successfully accomplishing this task will be given extra credit (and a complete psychiatric examination)." (Then again, one of Tannenbaum's students did infamously go on to buy a bag of 386's and implement an OS).
As the adderall wears off and nitrogenated liquid waste distends my innards, I grow proportionately less interested in continuing this review. Summary: if you're going to read one advanced text on processor architecture this semester, H&P4'll cure what ails ye.
(0) This is, of course, terminally brain-damaged. You solve this by making tests count for 100% of the grade (preferably in the form of a single, cumulative final), not by propping up a textbook-publishing industry having all the appeal of highly industrialized gang rape. Is this the purchasing of textbooks, or the Eastern Front circa early '45? Did we lose a war?
Now that Moore's law is at an end, how do we make computers faster? 1: The Memory Hierarchy (caches). This works pretty well, but caches can only be so large before they get slow. 2: Instruction-Level Parallelism (instruction pipelines). This is horribly complicated, doesn't work particularly well, and is subject to side channel attacks. But it doesn't require any work on the part of developers. 3: Data-Level Parallelism (GPUs). This works great for specialized applications. 4: Thread-Level Parallelism (multi-cores). Adding cores works if you don't require a lot of cross-core communication. If you do, memory coherence will become the bottleneck. 5: Request-Level Parallelism (WSCs). The cloud works well for decorrelated workloads that can be run on multi-tenant servers. 6: Domain-Specific Architectures (TPUs). If you've got something straightforward and computationally expensive (like DNN training / inference), build your own chip.
An outstanding follow-up to Computer Organization and Design, Computer Architecture: A Quantitative Approach is exactly what it says on the tin: A Quantitative Approach to Computer Architecture. Shocking, I know.
I found Chapter One to be fairly uninteresting, the description of memory models in Chapter 2 and advanced pipelining concepts in Chapter 3 (particularly the discussion of Tomasulo's Algorithm) enlightening, but Chapter 4 is where the book really heats up. It starts light with vector and SIMD approaches before discussing GPU Architecture. If you've ever been mystified by how the graphics card does its job and whether your problem maps to a GPU Compute approach, read Chapter Four of this book.
Chapter 5's discussion of Thread-Level Parallelism was interesting, but not as riveting as Chapter 4, but Chapter 6 picks up again with a discussion of Warehouse Scale Computers. I didn't know that I'd care about how WSCs work, the concerns associated with them, and, well, the sheer technological wonders that they actually are, akin to a power plant or water treatment facility! Even if you read nothing else in the book, Chapter 6 is worth a read all on its own.
In addition to Appendices A, B, and C, which are included in the hardcopy, there are also online appendices D through L. As of this writing, I'm still working through Appendix F: Interconnection Networks, because the online appendices somehow don't count as part of the book in my mind, probably because they comprise more pages among them than the whole hardcopy textbook, including the references and indices.
All in all, Computer Architecture: A Quantitative Approach is a five-star book, appropriate for anyone who wants the gritty details of how hardware does its job, provided that the prospective reader started with this book's younger sibling, Computer Organization and Design, by the same authors.
Hennessy and Patterson have a lot of great numbers and facts in the book, which help ground the theory of computer architecture in reality. There's an excellent mix of content-driven chapters and helpful appendices. The only thing holding this book back from a perfect review is the heavy and obvious bias towards their own MIPS architecture, when in the modern world greater attention to x86 would probably have been more helpful.
A must-read for understanding how computers and performance optimizations work under the hood. I scanned through the book (didn't do all the exercises and such) but still learned a ton about the context (Moore's Law), different levels of parallelisms and the use cases and hardwares associated, as well as the future of optimizations such as domain-specific architectures. Will definitely re-read for more in-depth takeaways in the future.
Definitely quantitative in its approach, which was sometimes too much for me, but definitely as advertised so I won't slight it for that. It's written in that humble sort of way with respect for the topics, and that's something I always appreciate. I found it was the most boring book ever, but occasionally I'd learn something so good that I couldn't stop reading it.
Sixth edition (with appendices) is dense. Extremely difficult read but enjoyed fully. If you are fairly new to the subject, I suggest ripes visualizer as a supplement (specially the six stage pipeline). Skim the chapters multiple times before diving in
I think I'm probably now in the wrong position to be reading this book, as I've already had the undergrad courses on it. This is a clear and detailed look at the whole spectrum of computer architecture. It even includes a chapter on disk storage, although event I find it very difficult to get excited about RAID and disk drives! This is a classic textbook on the subject. There's not much more to say.
This is a comprehensive textbook on ISA/architecture design, with very recent examples (i7, cortex-a8), and explains the problems you can see with the current hardware and how some of those get solved. There's a good chapter on GPUs, and not-that-good chapter on "warehouse-sized-computers" (e.g. a google datacenter).
It's good to do at least a cursory read, just to have an idea what happens below the compiler/compiled code/assembly.
Comp arch., is a fascinating subject; this book which borders on "graduate", covers much of what remains, from comp. design and org., in sufficient detail, to grasp, certain basics. The section on domain specific ASIC designs, is especially helpful, as we approach, the five angstroms limit. Recommended.
Arguably one of the most in depth and thoughtful books on computer architecture I have ever had the pleasure to read. A book I keep coming back too. Chapter 2 Memory Hierarchy and 6 Warehouse-Scale Computers are must reads. Highly, highly recommended.