Writing Testbenches: Functional Verification of HDL Models

by Janick Bergeron

This text first introduces the necessary concepts and tools of verification, then describes a process for carrying out an effective functional verification of a design. This book also presents techniques for applying a stimulus and monitoring the response of a design by abstracting the operations using bus-functional models. The architecture of testbenches built around these bus-functional models is important for minimizing development and maintenance effort. Behavioural modelling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioural modelling is synonymous with synthesizeable or RTL modelling. In this book, the term behavioural is used to describe any model that adequately emulates the functionality of a design, usually using non-synthesizeable constructs and coding style. The text focuses on the functional verification of hardware designs using either VHDL or Verilog.

384 pages, Hardcover

First published January 1, 2000