CMOS Sram Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware Sram Design and Test

by Andrei Pavlov, Manoj Sachdev

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The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

Hardcover, 212 pages

Published June 23rd 2008 by Springer

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